1. Field of the Invention
This disclosure relates to a transistor, a semiconductor device, and a method of fabricating the semiconductor device and, more particularly, to a transistor having an asymmetric channel region, a semiconductor device including the transistor, and a method of fabricating the semiconductor device.
2. Description of the Related Art
In semiconductor devices, discrete devices, such as MOS transistors, have been widely employed as switching devices. As integration of semiconductor devices increases, the MOS transistors are being gradually scaled down. As a result, channel lengths of the MOS transistors are reduced, which may cause a short channel effect.
Implanting channel ions into a channel region at a high concentration is generally used to prevent a threshold voltage from being reduced due to the short channel effect. However, implanting channel ions at a high concentration increases the channel resistance, resulting in degraded current driving capability. Furthermore, the concentration increase of the channel ions is accompanied by an increase of an electric field between the channel region and source/drain regions. Accordingly, the leakage current increases between the channel region and the source/drain regions. In particular, where a capacitor that stores charges is connected to the source region or the drain region as in a DRAM device, the increase of the leakage current deteriorates refresh characteristics of the device.
There is, therefore, a need to prevent the short channel effect due to reduction in the channel length of the MOS transistor and preventing the refresh characteristics from being deteriorated due to the increase of the leakage current. In particular, there is a need to maintain a constant threshold voltage while reducing an electric field between the channel region and the source/drain regions to which the capacitor is connected.
A method of fabricating an asymmetric source/drain transistor is taught in U.S. Pat. No. 6,596,594 to Guo, et al., entitled “Method of Fabricating Field Effect Transistor (FET) Device with Asymmetric Channel Region and Asymmetric Source and Drain Regions.”
Embodiments of the invention address the above and other disadvantages of the conventional art.